View MAX106_2789.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

19-1486; Rev 0; 7/99
5V, 600Msps, 8-Bit ADC with On-Chip 2.2GHz Bandwidth Track/Hold Amplifier
General Description
The MAX106 PECL-compatible, 600Msps, 8-bit analog-todigital converter (ADC) allows accurate digitizing of analog signals with bandwidths to 2.2GHz. Fabricated on Maxim's proprietary advanced GST-2 bipolar process, the MAX106 integrates a high-performance track/hold (T/H) amplifier and a quantizer on a single monolithic die. The innovative design of the internal T/H, which has an exceptionally wide 2.2GHz full-power input bandwidth, results in high, 7.6 effective bits performance at the Nyquist frequency. A fully differential comparator design and decoding circuitry combine to reduce out-ofsequence code errors (thermometer bubbles or sparkle codes) and provide excellent metastable performance of one error per 1027 clock cycles. Unlike other ADCs, which can have errors that result in false full- or zero-scale outputs, the MAX106 limits the error magnitude to 1LSB. The analog input is designed for either differential or single-ended use with a 250mV input voltage range. Dual, differential, PECL-compatible output data paths ensure easy interfacing and include an 8:16 demultiplexer feature that reduces output data rates to one-half the sampling clock rate. The PECL outputs can be operated from any supply between +3V to +5V for compatibility with +3.3V or +5V referenced systems. Control inputs are provided for interleaving additional MAX106 devices to increase the effective system sampling rate. The MAX106 is packaged in a 25mm x 25mm, 192-contact Enhanced Super-Ball-Grid Array (ESBGATM), and is specified over the commercial (0C to +70C) temperature range. For a pin-compatible higher speed upgrade, refer to the MAX104 (1Gsps) and MAX108 (1.5Gsps) data sheets. o 600Msps Conversion Rate o 2.2GHz Full-Power Analog Input Bandwidth o 7.6 Effective Bits at fIN = 300MHz (Nyquist frequency) o 0.25LSB INL and DNL o 50 Differential Analog Inputs o 250mV Input Signal Range o On-Chip, +2.5V Precision Bandgap Voltage Reference o Latched, Differential PECL Digital Outputs o Low Error Rate: 10-27 Metastable States o Selectable 8:16 Demultiplexer o Internal Demux Reset Input with Reset Output o 192-Contact ESBGA o Pin Compatible with Faster MAX104/MAX108
Features
MAX106
Ordering Information
PART MAX106CHC TEMP. RANGE 0C to +70C PIN-PACKAGE 192 ESBGA
192-Contact ESBGA Ball Assignment Matrix
TOP VIEW
Applications
Digital RF/IF Signal Processing Direct RF Downconversion High-Speed Data Acquisition Digital Oscilloscopes High-Energy Physics Radar/ECM Systems ATE Systems
MAX106
Typical Operating Circuit appears at end of data sheet.
ESBGA is a trademark of Amkor/Anam.
ESBGA
________________________________________________________________ Maxim Integrated Products
1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800. For small orders, phone 1-800-835-8769.
5V, 600Msps, 8-Bit ADC with On-Chip 2.2GHz Bandwidth Track/Hold Amplifier MAX106
ABSOLUTE MAXIMUM RATINGS
VCCA to GNDA .........................................................-0.3V to +6V VCCD to GNDD.........................................................-0.3V to +6V VCCI to GNDI ............................................................-0.3V to +6V VCCO to GNDD ........................................-0.3V to (VCCD + 0.3V) AUXEN1, AUXEN2 to GND .....................-0.3V to (VCCD + 0.3V) VEE to GNDI..............................................................-6V to +0.3V Between GNDs......................................................-0.3V to +0.3V VCCA to VCCD .......................................................-0.3V to +0.3V VCCA to VCCI.........................................................-0.3V to +0.3V PECL Digital Output Current ...............................................50mA REFIN to GNDR ........................................-0.3V to (VCCI + 0.3V) REFOUT Current ................................................+100A to -5mA ICONST, IPTAT to GNDI .......................................-0.3V to +1.0V TTL/CMOS Control Inputs (DEMUXEN, DIVSELECT) ....................-0.3V to (VCCD + 0.3V) RSTIN+, RSTIN- ......................................-0.3V to (VCCO + 0.3V) VOSADJ Adjust Input ................................-0.3V to (VCCI + 0.3V) CLK+ to CLK- Voltage Difference..........................................3V CLK+, CLK-.....................................(VEE - 0.3V) to (GNDD + 1V) CLKCOM.........................................(VEE - 0.3V) to (GNDD + 1V) VIN+ to VIN- Voltage Difference ............................................2V VIN+, VIN- to GNDI................................................................2V Continuous Power Dissipation (TA = +70C) 192-Contact ESBGA (derate 61mW/C above +70C) ...4.88W (with heatsink and 200LFM airflow, derate 106mW/C above +70C) ....................................8.48W Operating Temperature Range MAX106CHC........................................................0C to +70C Operating Junction Temperature.....................................+150C Storage Temperature Range .............................-65C to +150C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCCA = VCCI = VCCD = +5.0V 5%, VEE = -5.0V 5%, VCCO = +3.0V to VCCD, REFIN connected to REFOUT, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) PARAMETER ACCURACY Resolution Integral Nonlinearity (Note 1) Differential Nonlinearity (Note 1) Missing Codes ANALOG INPUTS Full-Scale Input Range (Note 1) Common-Mode Input Range Input Resistance Input Resistance Temperature Coefficient VOS ADJUST CONTROL INPUT Input Resistance (Note 2) Input VOS Adjust Range REFERENCE INPUT AND OUTPUT Reference Output Voltage Reference Output Load Regulation Reference Input Resistance REFOUT Driving REFIN input only 2.475 2.50 2.525 5 4 5 V mV k RVOS VOSADJ = 0 to 2.5V 14 4 25 5.5 k LSB VFSR VCM RIN TCR Signal + offset w.r.t. GNDI VIN+ and VIN- to GNDI, TA = +25C 49 475 500 0.8 50 150 51 525 mVp-p V ppm/C RES INL DNL TA = +25 C TA = +25 C No missing codes guaranteed 8 -0.5 -0.5 0.25 0.25 0.5 0.5 None Bits LSB LSB Codes SYMBOL CONDITIONS MIN TYP MAX UNITS
REFOUT 0 < ISOURCE < 2.5mA RREF Referenced to GNDR
2
_______________________________________________________________________________________
5V, 600Msps, 8-Bit ADC with On-Chip 2.2GHz Bandwidth Track/Hold Amplifier
DC ELECTRICAL CHARACTERISTICS (continued)
(VCCA = VCCI = VCCD = +5.0V 5%, VEE = -5.0V 5%, VCCO = +3.0V to VCCD, REFIN connected to REFOUT, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.) PARAMETER CLOCK INPUTS (Note 3) Clock Input Resistance Input Resistance Temperature Coefficient High-Level Input Voltage Low-Level Input Voltage High-Level Input Current Low-Level Input Current DEMUX RESET INPUT (Note 4) Digital Input High Voltage Digital Input Low Voltage PECL DIGITAL OUTPUTS (Note 5) Digital Output High Voltage Digital Output Low Voltage POWER REQUIREMENTS Positive Analog Supply Current Positive Input Supply Current Negative Input Supply Current Digital Supply Current Output Supply Current (Note 6) Power Dissipation (Note 6) Common-Mode Rejection Ratio (Note 7) Positive Power-Supply Rejection Ratio (Note 8) Negative Power-Supply Rejection Ratio (Note 8) ICCA ICCI IEE ICCD ICCO PDISS CMRR PSRR+ PSRRVIN+ = VIN- = 0.1V (Note 9) (Note 10) 40 40 40 -290 480 108 -210 205 75 5.25 68 73 68 340 115 780 150 mA mA mA mA mA W dB dB dB VOH VOL -1.025 -1.810 -0.880 -1.620 V V VIH VIL -1.165 -1.475 V V RCLK TCR CLK+ and CLK- to CLKCOM, TA = +25C 48 50 150 52 ppm/C SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX106
TTL/CMOS CONTROL INPUTS (DEMUXEN, DIVSELECT) VIH VIL IIH IIL VIH = 2.4V VIL = 0 -1 2.0 0.8 50 1 V V A A
_______________________________________________________________________________________
3
5V, 600Msps, 8-Bit ADC with On-Chip 2.2GHz Bandwidth Track/Hold Amplifier MAX106
AC ELECTRICAL CHARACTERISTICS
(VCCA = VCCI = VCCD = +5.0V, VEE = -5.0V, VCCO = +3.3V, REFIN connected to REFOUT, fS = 600Msps, fIN at -1dBFS, TA = +25C, unless otherwise noted.) PARAMETER ANALOG INPUT Analog Input Full-Power Bandwidth Analog Input VSWR Transfer Curve Offset DYNAMIC SPECIFICATIONS ENOB600 Effective Number of Bits (Note 11) ENOB300 ENOB125 SNR600 Signal-to-Noise Ratio (No Harmonics) SNR300 SNR125 THD600 Total Harmonic Distortion (Note 12) THD300 THD125 SFDR600 Spurious-Free Dynamic Range SFDR300 SFDR125 SINAD600 Signal-to-Noise Ratio and Distortion (Note 11) SINAD300 SINAD125 Two-Tone Intermodulation IMD fIN = 600MHz fIN = 300MHz fIN = 125MHz fIN = 600MHz fIN = 300MHz fIN = 125MHz fIN = 600MHz fIN = 300MHz fIN = 125MHz fIN = 600MHz fIN = 300MHz fIN = 125MHz fIN = 600Hz fIN = 300MHz fIN = 125MHz Differential Single-ended Differential Single-ended Differential Single-ended Differential Single-ended Differential Single-ended Differential Single-ended Differential Single-ended Differential Single-ended Differential Single-ended Differential Single-ended Differential Single-ended Differential Single-ended Differential Single-ended Differential Single-ended Differential Single-ended 46.3 45.7 63.0 52.0 -63.0 -52.0 44.2 43.8 7.4 7.3 7.63 7.62 7.65 7.65 7.74 7.74 46.8 46.8 47.1 47.1 47.4 47.4 -57.0 -56.1 -56.5 -56.5 -67.5 -67.5 57.4 56.7 57.5 57.4 69.9 69.9 47.7 47.6 47.8 47.8 48.4 48.4 -61.8 dB dB dB dB dB Bits BW-3dB VSWR VOS fIN = 500MHz VOSADJ control input open -1.5 2.2 1.1:1 0 1.5 GHz V/V LSB SYMBOL CONDITIONS MIN TYP MAX UNITS
fIN1 = 124MHz, fIN2 = 126MHz, at -7dB below full scale
4
_______________________________________________________________________________________
5V, 600Msps, 8-Bit ADC with On-Chip 2.2GHz Bandwidth Track/Hold Amplifier
AC ELECTRICAL CHARACTERISTICS (continued)
(VCCA = VCCI = VCCD = +5.0V, VEE = -5.0V, VCCO = +3.3V, REFIN connected to REFOUT, fS = 600Msps, fIN at -1dBFS, TA = +25C, unless otherwise noted.) PARAMETER TIMING CHARACTERISTICS Maximum Sample Rate Clock Pulse Width Low Clock Pulse Width High Aperture Delay Aperture Jitter Reset Input Data Setup Time (Note 13) Reset Input Data Hold Time (Note 13) CLK to DREADY Propagation Delay DREADY to DATA Propagation Delay (Note 14) DATA Rise Time DATA Fall Time DREADY Rise Time DREADY Fall Time Primary Port Pipeline Delay Auxiliary Port Pipeline Delay fMAX tPLW tPWH tAD tAJ tSU tHD tPD1 tPD2 tRDATA tFDATA tRDREADY tFDREADY tPDP tPDA Figure 17 Figure 17 Figure 17 Figure 4 Figure 15 Figure 15 Figure 17 Figure 17 20% to 80%, CL = 3pF 20% to 80%, CL = 3pF 20% to 80%, CL = 3pF 20% to 80%, CL = 3pF Figures 6, 7, 8 Figures 6, 7, 8 DIV1, DIV2 modes DIV4 mode DIV1, DIV2 modes DIV4 mode -50 0 0 2.2 150 420 360 220 180 7.5 7.5 8.5 9.5 350 600 0.75 0.75 100 < 0.5 5 Msps ns ns ps ps ps ps ns ps ps ps ps ps Clock Cycles Clock Cycles SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX106
Note 1: Static linearity parameters are computed from a "best-fit" straight line through the code transition points. The full-scale range (FSR) is defined as 256 * slope of the line. Note 2: The offset control input is a self-biased voltage divider from the internal +2.5V reference voltage. The nominal open-circuit voltage is +1.25V. It may be driven from an external potentiometer connected between REFOUT and GNDI. Note 3: The clock input's termination voltage can be operated between -2.0V and GNDI. Observe the absolute maximum ratings on the CLK+ and CLK- inputs. Note 4: Input logic levels are measured with respect to the VCCO power-supply voltage. Note 5: All PECL digital outputs are loaded with 50 to VCCO - 2.0V. Measurements are made with respect to the VCCO powersupply voltage. Note 6: The current in the VCCO power supply does not include the current in the digital output's emitter followers, which is a function of the load resistance and the VTT termination voltage. Note 7: Common-mode rejection ratio is defined as the ratio of the change in the transfer-curve offset voltage to the change in the common-mode voltage, expressed in dB. Note 8: Measured with the positive supplies tied to the same potential, VCCA = VCCD = VCCI. VCC varies from +4.75V to +5.25V. Note 9: VEE varies from -5.25V to -4.75V. Note 10: Power-supply rejection ratio is defined as the ratio of the change in the transfer-curve offset voltage to the change in power supply voltage, expressed in dB. Note 11: Effective number of bits (ENOB) and signal-to-noise plus distortion (SINAD) are computed from a curve fit referenced to the theoretical full-scale range.
_______________________________________________________________________________________
5
5V, 600Msps, 8-Bit ADC with On-Chip 2.2GHz Bandwidth Track/Hold Amplifier MAX106
Note 12: Total harmonic distortion (THD) is computed from the first five harmonics. Note 13: Guaranteed by design with a reset pulse width of one clock period or longer. Note 14: The DREADY to DATA propagation delay is measured from the 50% point on the rising edge of the DREADY signal (when the output data changes) to the 50% point on a data output bit. This places the falling edge of the DREADY signal in the middle of the data output valid window, within the differences between the DREADY and DATA rise and fall times, which gives maximum setup and hold time for latching external data latches.
Typical Operating Characteristics
(VCCA = VCCI = VCCD = +5.0V, VEE = -5.0V, VCCO = +3.3V, REFIN connected to REFOUT, fS = 600Msps, TA = +25C, unless otherwise noted.)
EFFECTIVE NUMBER OF BITS vs. ANALOG INPUT FREQUENCY (SINGLE-ENDED ANALOG INPUT DRIVE)
MAX106 toc01
MAX106 toc02
-6dBFS 7.75 7.50 ENOB (Bits) 7.25 7.00 6.75 6.50 10 100
-12dBFS
-6dBFS 7.75 7.50 ENOB (Bits) 7.25 7.00
-12dBFS
49 -1dBFS -1dBFS SINAD (dB)
-6dBFS
-12dBFS
48 -1dBFS 47
6.75 6.50 1000 10 100 ANALOG INPUT FREQUENCY (MHz) 1000 ANALOG INPUT FREQUENCY (MHz) 46 10 100 ANALOG INPUT FREQUENCY (MHz) 1000
MAX106 toc04
MAX106 toc05
-1dBFS 46 -6dBFS
-1dBFS 46 -6dBFS
49 SINAD (dB)
-6dBFS
-12dBFS SNR (dB)
48 -1dBFS 47
38
SNR (dB)
42
42
-12dBFS
38
-12dBFS
34
34
46 10 100 ANALOG INPUT FREQUENCY (MHz) 1000
30 10 100 ANALOG INPUT FREQUENCY (MHz) 1000
30 10 100 ANALOG INPUT FREQUENCY (MHz) 1000
6
_______________________________________________________________________________________
MAX106 toc06
50
SIGNAL-TO-NOISE PLUS DISTORTION vs. ANALOG INPUT FREQUENCY (DIFFERENTIAL ANALOG INPUT DRIVE)
50
SIGNAL-TO-NOISE RATIO vs. ANALOG INPUT FREQUENCY (SINGLE-ENDED ANALOG INPUT DRIVE)
50
SIGNAL-TO-NOISE RATIO vs. ANALOG INPUT FREQUENCY (DIFFERENTIAL ANALOG INPUT DRIVE)
MAX106 toc03
8.00
8.00
EFFECTIVE NUMBER OF BITS vs. ANALOG INPUT FREQUENCY (DIFFERENTIAL ANALOG INPUT DRIVE)
50
SIGNAL-TO-NOISE PLUS DISTORTION vs. ANALOG INPUT FREQUENCY (SINGLE-ENDED ANALOG INPUT DRIVE)
5V, 600Msps, 8-Bit ADC with On-Chip 2.2GHz Bandwidth Track/Hold Amplifier MAX106
Typical Operating Characteristics (continued)
(VCCA = VCCI = VCCD = +5.0V, VEE = -5.0V, VCCO = +3.3V, REFIN connected to REFOUT, fS = 600Msps, TA = +25C, unless otherwise noted.)
SPURIOUS-FREE DYNAMIC RANGE vs. ANALOG INPUT FREQUENCY (SINGLE-ENDED ANALOG INPUT DRIVE)
MAX106 toc09
-1dBFS 70 -6dBFS
70
-1dBFS
MAX106 toc10
7.75 7.50
SFDR (dB)
SFDR (dB)
65
65
-6dBFS
ENOB (Bits)
7.25 7.00
60
60
55
-12dBFS
55
-12dBFS
6.75 fIN = 125MHz, -1dBFS 6.50
50 10 100 ANALOG INPUT FREQUENCY (MHz) 1000
50 10 100 ANALOG INPUT FREQUENCY (MHz) 1000
100 CLOCK FREQUENCY (MHz)
600
EFFECTIVE NUMBER OF BITS vs. CLOCK POWER
DIFFERENTIAL CLOCK DRIVE 7.75 7.50 ENOB (Bits) 7.25 7.00 6.75 fIN = 125MHz, -1dBFS 6.50 -12 -10 -8 -6 -4 -2 0 2 4 6 8 10 CLOCK POWER PER SIDE (dBm) 6.50 4.50 SINGLE-ENDED CLOCK DRIVE ENOB (Bits)
MAX106toc12
EFFECTIVE NUMBER OF BITS vs. VCCI = VCCA = VCCD
MAX106toc13
EFFECTIVE NUMBER OF BITS vs. VEE
MAX106toc14
8.00
8.00 7.75 7.50 7.25 7.00 6.75 fIN = 125MHz, -1dBFS 4.70 4.90 5.10 5.30
8.00 7.75 7.50 ENOB (Bits) 7.25 7.00 6.75 6.50 -5.50
5.50
-5.30
-5.10
-4.90
-4.70
-4.50
VCC (V)
VEE (V)
SPURIOUS-FREE DYNAMIC RANGE vs. CLOCK POWER
MAX106 toc15
SPURIOUS-FREE DYNAMIC RANGE vs. VCCI = VCCA = VCCD
MAX106 toc16
SPURIOUS-FREE DYNAMIC RANGE vs. VEE
74 73 72 SFDR (dB) 71 70 69 68 67 66 65 fIN = 125MHz, -1dBFS
MAX106 toc17
75 73 71 69 SFDR (dB) DIFFERENTIAL CLOCK DRIVE SINGLE-ENDED CLOCK DRIVE
75 74 73 72 SFDR (dB) 71 70 69 68 67 fIN = 125MHz, -1dBFS
75
67 65 63 61 59 57 55
fIN = 125MHz, -1dBFS -12 -10 -8 -6 -4 -2 0 2 4 6 8 10
66 65 4.50 4.70 4.90 5.10 5.30 5.50
-5.50
-5.30
-5.10
-4.90
-4.70
-4.50
CLOCK POWER PER SIDE (dBm)
VCC (V)
VEE (V)
_______________________________________________________________________________________
7
MAX106 toc11
75
75
SPURIOUS-FREE DYNAMIC RANGE vs. ANALOG INPUT FREQUENCY (DIFFERENTIAL ANALOG INPUT DRIVE)
EFFECTIVE NUMBER OF BITS vs. CLOCK FREQUENCY
8.00
5V, 600Msps, 8-Bit ADC with On-Chip 2.2GHz Bandwidth Track/Hold Amplifier MAX106
Typical Operating Characteristics (continued)
(VCCA = VCCI = VCCD = +5.0V, VEE = -5.0V, VCCO = +3.3V, REFIN connected to REFOUT, fS = 600Msps, TA = +25C, unless otherwise noted.)
TOTAL HARMONIC DISTORTION vs. VEE
MAX106 toc18
TOTAL HARMONIC DISTORTION vs. VCCI = VCCA = VCCD
MAX106 toc19
-61 -62 -63 THD (dB)
fIN = 125MHz, -1dBFS
-61 -62 -63 THD (dB) -64 -65 -66 -67 -68 -69 -70
FUNDAMENTAL -25.6 AMPLITUDE (dB)
ENOB = 7.75 BITS SNR = 47.5dB THD = -68.8dB SFDR = 70.8dB H3 H2
-64 -65 -66 -67 -68 -69 -70 -5.50 -5.30 -5.10 -4.90 -4.70 -4.50 VEE (V)
-51.2
-76.8
-102.4
-128.0 4.50 4.70 4.90 5.10 5.30 5.50 0 60 120 180 240 300 VCC (V) ANALOG INPUT FREQUENCY (MHz)
FFT PLOT (fIN = 304.4677734MHz, RECORD LENGTH 8192)
MAX106 toc21
FFT PLOT (fIN = 1001.8798828MHz, RECORD LENGTH 8192)
MAX106 toc22
TWO-TONE INTERMODULATION DISTORTION FFT PLOT (RECORD LENGTH 8192, -7dB BELOW FULL-SCALE)
f1 -25.6 AMPLITUDE (dB) f2 f1 = 123.9990235MHz f2 = 126.0498047MHz SFDR = 61.6dB
MAX106 toc23
0 ENOB = 7.67 BITS SNR = 47.2dB THD = -56.8dB SFDR = 57.4dB FUNDAMENTAL
0
-25.6 AMPLITUDE (dB)
-25.6 AMPLITUDE (dB)
-51.2 H2 -76.8
H3
-51.2
FUNDAMENTAL ENOB = 7.48 BITS SNR = 46.0dB THD = -52.9dB SFDR = 54.7dB H3
0
H2
-51.2
(2 x f1) - f2
(2 x f2) - f1
-76.8
-76.8
-102.4
-102.4
-102.4
-128.0 0 60 120 180 240 300 ANALOG INPUT FREQUENCY (MHz)
-128.0 0 60 120 180 240 300 ANALOG INPUT FREQUENCY (MHz)
-128.0 0 60 120 180 240 300 ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT BANDWIDTH -6dB BELOW FULL-SCALE
MAX106toc24
ANALOG INPUT BANDWIDTH FULL-POWER
MAX106toc25
INTEGRAL NONLINEARITY vs. OUTPUT CODE (LOW-FREQUENCY SERVO-LOOP DATA)
0.4 0.3 0.2 INL (LSB)
MAX106 toc26
-5
0
0.5
-6 AMPLITUDE (dB) AMPLITUDE (dB)
-1
-7
-2
0.1 0 -0.1 -0.2
-8
-3
-9 SMALL-SIGNAL BANDWIDTH = 2.4GHz -10 500 1500 2500 ANALOG INPUT FREQUENCY (MHz)
-4 FULL-POWER BANDWIDTH = 2.2GHz -5 500 1500 2500 ANALOG INPUT FREQUENCY (MHz)
-0.3 -0.4 -0.5 0 32 64 96 128 160 192 224 256 OUTPUT CODE
8
_______________________________________________________________________________________
MAX106 toc20
-60
-60
FFT PLOT (fIN = 125.1708984MHz, RECORD LENGTH 8192)
0
5V, 600Msps, 8-Bit ADC with On-Chip 2.2GHz Bandwidth Track/Hold Amplifier MAX106
Typical Operating Characteristics (continued)
(VCCA = VCCI = VCCD = +5.0V, VEE = -5.0V, VCCO = +3.3V, REFIN connected to REFOUT, fS = 600Msps, TA = +25C, unless otherwise noted.)
DIFFERENTIAL NONLINEARITY vs. OUTPUT (LOW-FREQUENCY SERVO-LOOP DATA)
MAX106 toc27
DREADY RISE/FALL TIME, DATA RISE/FALL TIME
MAX106 toc28
VOLTAGE STANDING-WAVE RATIO vs. ANALOG INPUT FREQUENCY
MAX106 toc29
0.5 0.4 0.3 0.2 DNL (LSB) 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 0 32 64 96
1.5
DREADY 200mV/div
1.4
VSWR DATA 200mV/div 128 160 192 224 256 500ps/div
1.3
1.2
1.1
1.0 0 500 1000 1500 2000 2500 OUTPUT CODE ANALOG INPUT FREQUENCY (MHz)
Pin Description
CONTACT A1-A4, A6, A7, B1, B2, C1, C2, D1, D2, D3, G1, H1, J2, J3, K1, K2, K3, L2, L3, M1, N1, T2, T3, U1, V1, V2, W1-W4 A5, B5, C5, H2, H3, M2, M3, U5, V5, W5 A8, B8, C8, U6, V6, W6 A9, B9, C9, U7, V7, W7 A10, E17, F2, P3, R17, R18 A11, B11, B16, B17, C11, C16, U9, U17, V9, V17, V18, W9 A12-A19, B19, C19, D19, E19, F19, G19, H19, J19, K19, L19, M19, N19, P19, T19, U19, V19, W10-W19 NAME GNDI FUNCTION Analog Ground--for T/H amplifier, clock distribution, bandgap reference, and reference amplifier. Analog Supply Voltage, +5V. Supplies T/H amplifier, clock distribution, bandgap reference, and reference amplifier. Analog Ground--For comparator array. Analog Supply Voltage, +5V. Supplies analog comparator array. Test Point. Do not connect. Digital Ground
VCCI GNDA VCCA TESTPOINT (T.P.) GNDD
VCCO
PECL Supply Voltage, +3V to +5V
_______________________________________________________________________________________
9
5V, 600Msps, 8-Bit ADC with On-Chip 2.2GHz Bandwidth Track/Hold Amplifier MAX106
Pin Description (continued)
CONTACT B3, B4, C3, C4, E3, F3, G2, G3, N2, N3, U2, U3, U4, V3, V4 B6, B7 B10, B18, C10, C17, C18, T17, T18, U8, U18, V8, W8 B12 B13 B14 B15 C6 C7 C12 C13 C14 C15 D17 NAME VEE GNDR VCCD P0+ A0+ P1+ A1+ REFIN REFOUT P0A0P1A1DIVSELECT FUNCTION Analog Supply Voltage, -5V. Supplies T/H amplifier, clock distribution, bandgap reference, and reference amplifier. Reference Ground. Must be connected to GNDI. Digital Supply Voltage, +5V Primary Output Data Bit 0 (LSB) Auxiliary Output Data Bit 0 (LSB) Primary Output Data Bit 1 Auxiliary Output Data Bit 1 Reference Input Reference Output Complementary Primary Output Data Bit 0 (LSB) Complementary Auxiliary Output Data Bit 0 (LSB) Complementary Primary Output Data Bit 1 Complementary Auxiliary Output Data Bit 1 TTL/CMOS Demux Divide-Selection Input 1: Decimation DIV4 mode 0: Demultiplexed DIV2 mode Tie to VCCO to power the auxiliary port. Tie to GNDD to power down. Die Temperature Measurement Test Point. See Die Temperature Measurement section. Die Temperature Measurement Test Point. See Die Temperature Measurement section. TTL/CMOS Demux Enable Control 1: Enable Demux 0: Disable Demux Offset Adjust Input Complementary Primary Output Data Bit 2 Primary Output Data Bit 2 Complementary Auxiliary Output Data Bit 2 Auxiliary Output Data Bit 2 Complementary Primary Output Data Bit 3 Primary Output Data Bit 3
D18 E1 E2
AUXEN2 ICONST IPTAT
E18 F1 F17 F18 G17 G18 H17 H18
DEMUXEN VOSADJ P2P2+ A2A2+ P3P3+
10
______________________________________________________________________________________
5V, 600Msps, 8-Bit ADC with On-Chip 2.2GHz Bandwidth Track/Hold Amplifier
Pin Description (continued)
CONTACT J1 J17 J18 K17 K18 L1 L17 L18 M17 M18 N17 N18 P1 P2 P17 P18 R1, R2, R3 R19 T1 U10 U11 U12 U13 U14 U15 U16 V10 V11 V12 V13 V14 V15 V16 NAME VINA3A3+ DREADYDREADY+ VIN+ P4P4+ A4A4+ P5P5+ CLKTESTPOINT (T.P.) A5A5+ CLKCOM AUXEN1 CLK+ RSTINRSTOUTORA7P7A6P6RSTIN+ RSTOUT+ OR+ A7+ P7+ A6+ P6+ FUNCTION Differential Input Voltage (-) Complementary Auxiliary Output Data Bit 3 Auxiliary Output Data Bit 3 Complementary Data-Ready Clock Data-Ready Clock Differential Input Voltage (+) Complementary Primary Output Data Bit 4 Primary Output Data Bit 4 Complementary Auxiliary Output Data Bit 4 Auxiliary Output Data Bit 4 Complementary Primary Output Data Bit 5 Primary Output Data Bit 5 Complementary Sampling Clock Input This contact must be connected to GNDI. Complementary Auxiliary Output Data Bit 5 Auxiliary Output Data Bit 5 50 Clock Termination Return Tie to VCCO to power the auxiliary port. Tie to GNDD to power down. Sampling Clock Input Complementary PECL Demux Reset Input Complementary PECL Reset Output Complementary PECL Overrange Bit Complementary Auxiliary Output Data Bit 7 (MSB) Complementary Primary Output Data Bit 7 (MSB) Complementary Auxiliary Output Data Bit 6 Complementary Primary Output Data Bit 6 PECL Demux Reset Input PECL Reset Output PECL Overrange Bit Auxiliary Output Data Bit 7 (MSB) Primary Output Data Bit 7 (MSB) Auxiliary Output Data Bit 6 Primary Output Data Bit 6
MAX106
______________________________________________________________________________________
11
5V, 600Msps, 8-Bit ADC with On-Chip 2.2GHz Bandwidth Track/Hold Amplifier MAX106
REF REF OUT IN BANDGAP REFERENCE +2.5V REFERENCE AMPLIFIER
VOSADJ
GNDR BIAS CURRENTS GNDI 50
MAX106
OVERRANGE BIT 2
DIFFERENTIAL PECL OUTPUTS OR
VIN+ VIN50 T/H AMPLIFIER
8-BIT FLASH ADC
2 16
AUXILIARY DATA PORT
A0-A7 16
PRIMARY DATA PORT
P0-P7 16
GNDI CLK+ 50 CLKCOM 50 CLKADC CLOCK DRIVER T/H CLOCK DRIVER LOGIC CLOCK DRIVER DEMUX CLOCK DRIVER
DATA READY CLOCK
DREADY 2
RSTIN+ RSTIN-
RESET INPUT DUAL LATCH
RESET PIPELINE
DELAYED RESET
DEMUX CLOCK GENERATOR
DEMUX RESET OUTPUT
RSTOUT 2
DEMUXEN DIVSELECT
Figure 1. Simplified Functional Diagram
Detailed Description
The MAX106 is an 8-bit, 600Msps flash ADC with onchip T/H amplifier and differential PECL-compatible outputs. The ADC (Figure 1) employs a fully differential 8-bit quantizer and a unique encoding scheme to limit metastable states to typically one error per 1027 clock cycles, with no error exceeding 1LSB max. An integrated 8:16 output demultiplexer simplifies interfacing to the part by reducing the output data rate to one-half the sampling clock rate. This demultiplexer has internal reset capability that allows multiple MAX106s to be time-interleaved to achieve higher effective sampling rates.
12
When clocked at 600Msps, the MAX106 provides a typical effective number of bits (ENOB) of 7.6 bits at an analog input frequency of 300MHz. The analog input of the MAX106 is designed for differential or single-ended use with a 250mV full-scale input range. In addition, this fast ADC features an on-board +2.5V precision bandgap reference. If desired, an external reference can also be used.
______________________________________________________________________________________
5V, 600Msps, 8-Bit ADC with On-Chip 2.2GHz Bandwidth Track/Hold Amplifier
Principle of Operation
The MAX106's flash or parallel architecture provides the fastest multibit conversion of all common integrated ADC designs. The key to this high-speed flash architecture is the use of an innovative, high-performance comparator design. The flash converter and downstream logic translate the comparator outputs into a parallel 8-bit output code and pass this binary code on to the optional 8:16 demultiplexer, where primary and auxiliary ports output PECL-compatible data at up to 300Msps per port (depending on how the demultiplexer section is set on the MAX106). The ideal transfer function appears in Figure 2.
OVERRANGE + 255 255 254 DIGITAL OUTPUT
MAX106
129 128 127 126 3 2 1 0 (-FS + 1LSB) 0 ANALOG INPUT (+FS - 1LSB) +FS
On-Chip Track/Hold Amplifier
As with all ADCs, if the input waveform is changing rapidly during conversion, ENOB and signal-to-noise ratio (SNR) specifications will degrade. The MAX106's on-chip, wide-bandwidth (2.2GHz) T/H amplifier reduces this effect and increases the ENOB performance significantly, allowing precise capture of fast analog data at high conversion rates. The T/H amplifier buffers the input signal and allows a full-scale signal input range of 250mV. The T/H amplifier's differential 50 input termination simplifies interfacing to the MAX106 with controlled impedance lines. Figure 3 shows a simplified diagram of the T/H amplifier stage internal to the MAX106. Aperture width, delay, and jitter (or uncertainty) are parameters that affect the dynamic performance of high-speed converters. Aperture jitter, in particular, directly influences SNR and limits the maximum slew rate (dV/dt) that can be digitized without a significant contribution of errors. The MAX106's innovative T/H amplifier design typically limits aperture jitter to less than 0.5ps.
Figure 2. Transfer Function
ALL INPUTS ARE ESD PROTECTED (NOT SHOWN IN THIS INPUT SAMPLING SIMPLIFIED DRAWING). AMPLIFIER BRIDGE VIN+ VIN50 50 CHOLD GNDI
BUFFER AMPLIFIER
TO COMPARATORS
GNDI CLK+ CLK50 CLKCOM 50 CLOCK SPLITTER
TO COMPARATORS
Figure 3. Internal Structure of the 2.2GHz T/H Amplifier
CLK CLK tAW ANALOG INPUT tAD tAJ SAMPLED DATA (T/H)
Aperture Width Aperture width (tAW) is the time the T/H circuit requires (Figure 4) to disconnect the hold capacitor from the input circuit (for instance to turn off the sampling bridge and put the T/H unit in hold mode). Aperture Jitter Aperture jitter (tAJ) is the sample-to-sample variation (Figure 4) in the time between the samples. Aperture Delay Aperture delay (tAD) is the time defined between the rising edge of the sampling clock and the instant when an actual sample is taken (Figure 4).
T/H
TRACK
HOLD TRACK APERTURE DELAY (tAD) APERTURE WIDTH (tAW) APERTURE JITTER (tAJ)
Figure 4. T/H Aperture Timing
______________________________________________________________________________________ 13
5V, 600Msps, 8-Bit ADC with On-Chip 2.2GHz Bandwidth Track/Hold Amplifier MAX106
Internal Reference
The MAX106 features an on-chip +2.5V precision bandgap reference that can be used by connecting REFOUT to REFIN. This connects the reference output to the positive input of the reference buffer. The buffer's negative input is internally tied to GNDR. GNDR must be connected to GNDI on the user's application board. REFOUT can source up to 2.5mA to supply external devices if required. An adjustable external reference can be used to adjust the ADC's full-scale range. To use an external reference supply, connect a high-precision reference to the REFIN pin and leave the REFOUT pin floating. In this configuration, REFOUT must not be simultaneously connected at any time, to avoid conflicts between the two references. REFIN has a typical input resistance of 5k and accepts input voltages of +2.5V 200mV. Using the MAX106's internal reference is recommended for best performance.
VCCO 500 500 A_+/P_+ DIFF. PAIR GNDD
A_-/P_-
1.8mA
GNDD
GNDD
Digital Outputs
The MAX106 provides data in offset binary format to differential PECL outputs. A simplified circuit schematic of the PECL output cell is shown in Figure 5. All PECL outputs are powered from VCCO, which may be operated from any voltage between +3.0V to VCCD for flexible interfacing with either +3.3V or +5V systems. The nominal VCCO supply voltage is +3.3V. All PECL outputs on the MAX106 are open-emitter types and must be terminated at the far end of each transmission line with 50 to VCCO - 2V. Table 1 lists all MAX106 PECL outputs and their functions.
Figure 5. Simplified PECL Output Structure
Demultiplexer Operation
The MAX106 features an internal data demultiplexer, which provides for three different modes of operation (see the following sections on Demultiplexed DIV2 Mode, Non-Demultiplexed DIV1 Mode, and Decimation DIV4 Mode) controlled by two TTL/CMOS-compatible inputs: DEMUXEN and DIVSELECT. DEMUXEN enables or disables operation of the internal 1:2 demultiplexer. A logic high on DEMUXEN activates the internal demultiplexer, and a logic low deactivates it. With the internal demultiplexer enabled, DIVSELECT controls the selection of the operational mode. DIVSELECT low selects demultiplexed DIV2 mode, and DIVSELECT high selects decimation DIV4 mode (Table 2).
Table 1. PECL Output Functions
PECL OUTPUT SIGNALS P0+ to P7+, P0- to P7A0+ to A7+, A0- to A7DREADY+, DREADYOR+, ORRSTOUT+, RSTOUTFUNCTION Primary-Port Differential Outputs from LSB to MSB. A "+" indicates the true value; a "-" denotes the complementary outputs. Auxiliary-Port Differential Outputs from LSB to MSB. A "+" indicates the true value; a "-" denotes the complementary outputs. Data-Ready Clock True and Complementary Outputs. These signal lines are used to latch the output data from the primary to the auxiliary output ports. Data changes on the rising edge of the DREADY clock. Overrange True and Complementary Outputs Reset Output True and Complementary Outputs
14
______________________________________________________________________________________
5V, 600Msps, 8-Bit ADC with On-Chip 2.2GHz Bandwidth Track/Hold Amplifier
Non-Demultiplexed DIV1 Mode The MAX106 may be operated at up to the full sampling rate (600Msps) in non-demultiplexed DIV1 mode (Table 2). In this mode, the internal demultiplexer is disabled and sampled data is presented to the primary port only, with the data repeated at the auxiliary port, but delayed by one clock cycle (Figure 6). Since the auxiliary output port contains the same data stream as the primary output port, the auxiliary port can be shut down to save power by connecting AUXEN1 and AUXEN2 to digital ground (GNDD). This powers down the internal bias cells and causes both outputs (true and complementary) of the auxiliary port to pull up to a logic-high level. To save additional power, the external 50 termination resistors connected to the PECL termiADC SAMPLE NUMBER CLKCLK CLK+ DREADY+ DREADY DREADYAUXILIARY DATA PORT PRIMARY DATA PORT n n+1 n+2 n+3 n+4 n n+1 n+2 n+3
nation power supply (VCCO - 2V) may be removed from all auxiliary output ports.
MAX106
Demultiplexed DIV2 Mode The MAX106 features an internally selectable DIV2 mode (Table 2) that reduces the output data rate to one-half of the sample clock rate. The demultiplexed outputs are presented in dual 8-bit format with two consecutive samples appearing in the primary and auxiliary output ports on the rising edge of the data-ready clock (Figure 7). The auxiliary data port contains the previous sample, and the primary output contains the most recent data sample. AUXEN1 and AUXEN2 must be connected to VCCO to power up the auxiliary port PECL output drives.
ADC SAMPLES ON THE RISING EDGE OF CLK+ n+4 n+5 n+6 n+7 n+8 n+9 n+10 n+11 n+12 n+13
n+1
n+2
n+3
n+4
n+5
NOTE: THE AUXILIARY PORT DATA IS DELAYED ONE ADDITIONAL CLOCK CYCLE FROM THE PRIMARY PORT DATA. GROUNDING AUXEN1 AND AUXEN2 WILL POWER DOWN THE AUXILIARY PORT TO SAVE POWER.
Figure 6. Non-Demuxed, DIV1-Mode Timing Diagram
ADC SAMPLE NUMBER CLKCLK CLK+ DREADY+ DREADY DREADYAUXILIARY DATA PORT PRIMARY DATA PORT n-1 n+1 n+3 n n+1 n+2 n+3
ADC SAMPLES ON THE RISING EDGE OF CLK+ n+4 n+5 n+6 n+7 n+8 n+9 n+10 n+11 n+12 n+13
n
n+2
n+4
NOTE: THE LATENCY TO THE PRIMARY PORT IS 7.5 CLOCK CYCLES, AND THE LATENCY TO THE AUXILIARY PORT IS 8.5 CLOCK CYCLES. BOTH THE PRIMARY AND AUXILIARY DATA PORTS ARE UPDATED ON THE RISING EDGE OF THE DREADY+ CLOCK.
Figure 7. Demuxed DIV2-Mode Timing Diagram
______________________________________________________________________________________ 15
5V, 600Msps, 8-Bit ADC with On-Chip 2.2GHz Bandwidth Track/Hold Amplifier
Decimation DIV4 Mode The MAX106 also offers a special decimated, demultiplexed output (Figure 8) that discards every other input sample and outputs data at one-quarter the input sampling rate for system debugging at slower output data rates. With an input clock of 600MHz, the effective output data rate will be reduced to 150MHz per output port in the DIV4 mode (Table 2). Since every other sample is discarded, the effective sampling rate is 300Msps.
MAX106
the OR bit will flag an overrange condition if either the primary or auxiliary port contains an overranged sample (Table 2). In non-demultiplexed DIV1 mode, the OR port will flag an overrange condition only when the primary output port contains an overranged sample.
Applications Information
Single-Ended Analog Inputs
The MAX106 T/H amplifier is designed to work at full speed for both single-ended and differential analog inputs (Figure 9). Inputs VIN+ and VIN- feature on-chip, laser-trimmed 50 termination resistors to provide excellent voltage standing-wave ratio (VSWR) performance.
Overrange Operation
A single differential PECL overrange output bit (OR+, OR-) is provided for both primary and auxiliary demultiplexed outputs. The operation of the overrange bit depends on the status of the internal demultiplexer. In demultiplexed DIV2 mode and decimation DIV4 mode,
ADC SAMPLE NUMBER CLKCLK CLK+ DREADY+ DREADY DREADYAUXILIARY DATA PORT PRIMARY DATA PORT n n+1 n+2 n+3
ADC SAMPLES ON THE RISING EDGE OF CLK+ n+4 n+5 n+6 n+7 n+8 n+9 n+10 n+11 n+12 n+13
n-2
n+2
n
n+4
NOTE: THE LATENCY TO THE PRIMARY PORT REMAINS 7.5 CLOCK CYCLES, WHILE THE LATENCY OF THE AUXILIARY PORT INCREASES TO 9.5 CLOCK CYCLES. THIS EFFECTIVELY DISCARDS EVERY OTHER SAMPLE AND REDUCES THE OUTPUT DATA RATE TO 1/4 THE SAMPLE CLOCK RATE.
Figure 8. Decimation DIV4-Mode Timing Diagram
Table 2. Demultiplexer Operation
DEMUXEN Low High High DIVSELECT X Low High DEMUX MODE DIV1 600Msps/port DIV2 300Msps/port DIV4 150Msps/port OVERRANGE-BIT OPERATION Flags overrange data appearing in the primary port only.
Flags overrange data appearing in either the primary or auxiliary port.
X = Don't care
16
______________________________________________________________________________________
5V, 600Msps, 8-Bit ADC with On-Chip 2.2GHz Bandwidth Track/Hold Amplifier MAX106
ANALOG INPUTS ARE ESD PROTECTED (NOT SHOWN IN THIS SIMPLIFIED DRAWING).
+2.8V +250mV
VIN+
VIN+ 50 GNDI 50 VIN-
500mVp-p FS ANALOG INPUT RANGE -250mV
500mV VINVIN = 250mV
0V
t
Figure 10a. Single-Ended Analog Input Signals
VEE
Figure 9. Simplified Analog Input Structure (Single-Ended/ Differential)
VIN+ +125mV 250mV FS ANALOG INPUT RANGE -125mV 250mV -250mV VIN-
In a typical single-ended configuration, the analog input signal (Figure 10a) enters the T/H amplifier stage at the in-phase input (VIN+), while the inverted phase input (VIN-) is reverse-terminated to GNDI with an external 50 resistor. Single-ended operation allows for an input amplitude of 250mV. Table 3 shows a selection of input voltages and their corresponding output codes for single-ended operation.
0V
t
Differential Analog Inputs
To obtain a full-scale digital output with differential input drive (Figure 10b), 250mVp-p must be applied between VIN+ and VIN- (VIN+ = +125mV and VIN- = -125mV). Midscale digital output codes (01111111 or 10000000) occur when there is no voltage difference between VIN+ and VIN-. For a zero-scale digital output code, the
Figure 10b. Differential Analog Input Signals
in-phase input (VIN+) must see -125mV and the inverted input (VIN-) must see +125mV. A differential input drive is recommended for best performance. Table 4 represents a selection of differential input voltages and their corresponding output codes.
Table 3. Ideal Input Voltage and Output Code Results for Single-Ended Operation
VIN+ +250mV +250mV - 1LSB 0V -250mV + 1LSB -250mV VIN0V 0V 0V 0V 0V OVERRANGE BIT 1 0 0 0 0 OUTPUT CODE 11111111 (full scale) 11111111 01111111 toggles 10000000 00000001 00000000 (zero scale) 17
______________________________________________________________________________________
5V, 600Msps, 8-Bit ADC with On-Chip 2.2GHz Bandwidth Track/Hold Amplifier MAX106
Table 4. Ideal Input Voltage and Output Code Results for Differential Operation
VIN+ +125mV +125mV - 0.5LSB 0V -125mV + 0.5LSB -125mV VIN-125mV -125mV + 0.5LSB 0V +125mV - 0.5LSB +125mV OVERRANGE BIT 1 0 0 0 0 OUTPUT CODE 11111111 (full scale) 11111111 01111111 toggles 10000000 00000001 00000000 (zero scale)
Offset Adjust
The MAX106 provides an analog input (VOSADJ) to compensate for system offsets. The offset adjust input is a self-biased voltage divider from the internal +2.5V precision reference. The nominal open-circuit voltage is onehalf the reference voltage. With an input resistance of typically 25k, this pin may be driven by an external 10k potentiometer (Figure 11) connected between REFOUT and GNDI to correct for offset errors. This control provides a typical 5.5LSB offset adjustment range.
REFOUT
MAX106
10k POT VOSADJ
Clock Operation
The MAX106 clock inputs are designed for either single-ended or differential operation (Figure 12) with flexible input drive requirements. Each clock input is terminated with an on-chip, laser-trimmed 50 resistor to CLKCOM (clock-termination return). The CLKCOM termination voltage can be connected anywhere between ground and -2V for compatibility with standard ECL drive levels. The clock inputs are internally buffered with a preamplifier to ensure proper operation of the data converter, even with small-amplitude sine-wave sources. The MAX106 was designed for single-ended, low-phasenoise sine-wave clock signals with as little as 100mV amplitude (-10dBm). This eliminates the need for an external ECL clock buffer and its added jitter.
GNDI
Figure 11. Offset Adjust with External 10k Potentiometer
CLK+ 50 CLKCOM 50 CLKGNDI +0.8V
Single-Ended Clock Inputs (Sine-Wave Drive) Excellent performance is obtained by AC- or DC-coupling a low-phase-noise sine-wave source into a single clock input (Figure 13a, Table 5). For proper DC balance, the undriven clock input should be externally 50 reverse-terminated to GNDI.
CLK INPUTS ARE ESD PROTECTED (NOT SHOWN IN THIS SIMPLIFIED DRAWING).
VEE
Figure 12. Simplified Clock Input Structure (Single-Ended/ Differential)
18 ______________________________________________________________________________________
5V, 600Msps, 8-Bit ADC with On-Chip 2.2GHz Bandwidth Track/Hold Amplifier
The dynamic performance of the data converter is essentially unaffected by clock-drive power levels from -10dBm (100mV clock signal amplitude) to +10dBm (1V clock signal amplitude). The MAX106 dynamic performance specifications are determined by a singleended clock drive of +4dBm (500mV clock signal amplitude). To avoid saturation of the input amplifier stage, limit the clock power level to a maximum of +10dBm.
Inputs (Sine-Wave Drive) for proper input amplitude requirements. Single-Ended Clock Inputs (ECL Drive) Configure the MAX106 for single-ended ECL clock drive by connecting the clock inputs as shown in Figure 13c (Table 5). A well-bypassed VBB supply (-1.3V) is essential to avoid coupling noise into the undriven clock input, which would degrade the dynamic performance. Differential Clock Inputs (ECL Drive) The MAX106 may be driven from a standard differential (Figure 13d, Table 5) ECL clock source by setting the clock termination voltage at CLKCOM to -2V. Bypass the clock-termination return (CLKCOM) as close to the ADC as possible with a 0.01F capacitor connected to GNDI.
MAX106
Differential Clock Inputs (Sine-Wave Drive) The advantages of differential clock drive (Figure 13b, Table 5) can be obtained by using an appropriate balun or transformer to convert single-ended sine-wave sources into differential drives. The precision on-chip laser-trimmed 50 clock-termination resistors ensure excellent amplitude matching. See Single-Ended Clock
+0.5V
CLK+ +0.5V CLK- = 0V
CLK+ CLK-
-0.5V
t
-0.5V
t
NOTE: CLKCOM = 0V
NOTE: CLKCOM = 0V
Figure 13a. Single-Ended Clock Input Signals
Figure 13b. Differential Clock Input Signals
-0.8V
CLK+ -0.8V CLK- = -1.3V
CLK+ CLK-
-1.8V
t
-1.8V
t
NOTE: CLKCOM = -2V
NOTE: CLKCOM = -2V
Figure 13c. Single-Ended ECL Clock Drive
Figure 13d. Differential ECL Clock Drive
19
______________________________________________________________________________________
5V, 600Msps, 8-Bit ADC with On-Chip 2.2GHz Bandwidth Track/Hold Amplifier MAX106
Table 5. DC-Coupled Clock Drive Options
CLOCK DRIVE Single-Ended Sine Wave Differential Sine Wave Single-Ended ECL Differential ECL CLK+ -10dBm to +4dBm -10dBm to +4dBm ECL Drive ECL Drive CLKExternal 50 to GNDI -10dBm to +4dBm -1.3V ECL Drive CLKCOM GNDI GNDI -2V -2V REFERENCE Figure 13a Figure 13b Figure 13c Figure 13d
AC-Coupling Clock Inputs The clock inputs CLK+ and CLK- can also be driven with positive referenced ECL (PECL) logic levels if the clock inputs are AC-coupled. Under this condition, connect CLKCOM to GNDI. Single-ended ECL/PECL/sinewave drive is also possible if the undriven clock input is reverse-terminated to GNDI through a 50 resistor in series with a capacitor whose value is identical to that used to couple the driven input.
RSTIN+
VCCO
50k
50k
Demux Reset Operation
The MAX106 features an internal 1:2 demultiplexer that reduces the data rate of the output digital data to onehalf the sample clock rate. Demux reset is necessary when interleaving multiple MAX106s and/or synchronizing external demultiplexers. The simplified block diagram of Figure 1 shows that the demux reset signal path consists of four main circuit blocks. From input to output, they are the reset input dual latch, the reset pipeline, the demux clock generator, and the reset output. The signals associated with the demux reset operation and the control of this section are listed in Table 6.
RSTIN-
20A
GNDD RESET INPUTS ARE ESD PROTECTED (NOT SHOWN ON THIS SIMPLIFIED DRAWING).
Reset Input Dual Latch The reset input dual-latch circuit block accepts differential PECL reset inputs referenced to the same VCCO power supply that powers the MAX106 PECL outputs. For applications that do not require a synchronizing reset, the reset inputs can be left open. In this case, they will self-bias to a proper level with internal 50k resistors and a 20A current source. This combination creates a -1V difference between RSTIN+ and RSTINto disable the internal reset circuitry. When driven with PECL logic levels terminated with 50 to (VCCO - 2V), the internal biasing network can easily be overdriven. Figure 14 shows a simplified schematic of the reset input structure. To properly latch the reset input data, setup (tSU) and data-hold times (tHD) must be met with respect to the rising edge of the sample clock. The timing diagram of Figure 15 shows the timing relationship of the reset input and sampling clock.
20
Figure 14. Simplified Reset Input Structure
RSTIN+ 50% RSTIN50%
tSU
tHD CLK+ 50% CLK-
Figure 15. Reset Input Timing Definitions
______________________________________________________________________________________
5V, 600Msps, 8-Bit ADC with On-Chip 2.2GHz Bandwidth Track/Hold Amplifier MAX106
Table 6. Demux Operating and Reset Control Signal
SIGNAL NAME CLK+, CLKDREADY+, DREADYRSTIN+, RSTINRSTOUT+, RSTOUTTYPE Sampling clock inputs Differential PECL outputs Differential PECL inputs Differential PECL outputs FUNCTION Master ADC Timing Signal. The ADC samples on the rising edge of CLK+. Data-Ready PECL Output. Output data changes on the rising edge of DREADY+. Demux Reset Input Signals. Resets the internal demux when asserted. Reset Outputs--for resetting additional external demux devices.
Reset Pipeline The next section in the reset signal path is the reset pipeline. This block adds clock latency cycles to the reset signal to match the latency of the converted analog data through the ADC. In this way, when reset data arrives at the RSTOUT+/RSTOUT- PECL output it will be time-aligned with the analog data present in the primary and auxiliary ports at the time the reset input was deasserted at RSTIN+/RSTIN-. Demux Clock Generator The demux clock generator creates the DIV1, DIV2, or DIV4 clocks required for the different modes of demux and non-demux operation. The TTL/CMOS control inputs DEMUXEN and DIVSELECT control the demuxed mode selection, as described in Table 2. The timing diagrams in Figures 16 and 17 show the output timing and data alignment in DIV1, DIV2, and DIV4 modes, respectively.
The phase relationship between the sampling clock at the CLK+/CLK- inputs and the data-ready clock at the DREADY+/DREADY- outputs will be random at device power-up. As with all divide-by-two circuits, two possible phase relationships exist between these clocks. The difference between the phases is the inversion of the DIV2/DREADY clock. The timing diagram in Figure 16 shows this relationship. Reset all MAX106 devices to a known DREADY phase after initial power-up for applications such as interleaving, where two or more MAX106 devices are used to achieve higher effective sampling rates. This synchronization is necessary to set the order of output samples between the devices. Resetting the converters accomplishes this synchronization. The reset signal is used to force the internal counter in the demux clock-generator block to a known phase state.
tPWH CLK+ 50% CLKtPD1 DREADY"PHASE 1" DREADY+ DREADY + 80% "PHASE 2" DREADY PRIMARY PORT DATA 20% 20% 80% 50% tFDREADY DREADY tPD2 tRDREADY AUXILIARY PORT DATA DREADY + CLK+ CLKtPD1
tPWL
DREADY + DREADY -
Figure 16. CLK and DREADY Timing in Demuxed DIV2 Mode Showing Two Possible DREADY Phases
Figure 17. Output Timing for All Modes (DIV1, DIV2, DIV4)
______________________________________________________________________________________
21
5V, 600Msps, 8-Bit ADC with On-Chip 2.2GHz Bandwidth Track/Hold Amplifier
Reset Output Finally, the reset signal is presented in differential PECL format to the last block of the reset signal path. RSTOUT+/RSTOUT- output the time-aligned reset signal used for resetting additional external demuxes in applications where further reduction in the output data rate is desired. Many demux devices require their reset signal to be asserted for several clock cycles while they are clocked. To accomplish this, the MAX106 DREADY clock will continue to toggle while RSTOUT is asserted.
When a single MAX106 device is used, no synchronizing reset is required since the order of the samples in the output ports is unchanged regardless of the phase of the DREADY clock. In DIV2 mode, the data in the auxiliary port is delayed by 8.5 clock cycles while the data in the primary port is delayed by 7.5 clock cycles. The older data is always in the auxiliary port, regardless of the phase of the DREADY clock. The reset output signal, RSTOUT, is delayed by one fewer clock cycle (6.5 clock cycles) than the primary port. The reduced latency of RSTOUT serves to mark
MAX106
the start of synchronized data in the primary and auxiliary ports. When the RSTOUT signal returns to a zero, the DREADY clock phase is reset. Since there are two possible phases of the DREADY clock with respect to the input clock, there are two possible timing diagrams to consider. The first timing diagram (Figure 18) shows the RSTOUT timing and data alignment of the auxiliary and primary output ports when the DREADY clock phase is already reset. For this example, the RSTIN pulse is two clock cycles long. Under this condition, the DREADY clock continues uninterrupted, as does the data stream in the auxiliary and primary ports. The second timing diagram (Figure 19) shows the results when the DREADY phase is opposite from the reset phase. In this case, the DREADY clock "swallows" a clock cycle of the sample clock, resynchronizing to the reset phase. Note that the data stream in the auxiliary and primary ports has reversed. Before reset was
ADC SAMPLE NUMBER CLKCLK CLK+ RESET INPUT tSU RSTINRSTIN+ DREADYDREADY DREADY+ AUXILIARY DATA PORT PRIMARY DATA PORT RESET OUT DATA PORT RSTOUTRSTOUT+ n n+1 n+2 n+3
ADC SAMPLES ON THE RISING EDGE OF CLK+ n+4 n+5 n+6 n+7 n+8 n+9 n+10 n+11 n+12 n+13
tHD
n-1
n+1
n+3
n
n+2
n+4
NOTE: THE LATENCY TO THE RESET OUTPUT IS 6.5 CLOCK CYCLES. THE LATENCY TO THE PRIMARY PORT IS 7.5 CLOCK CYCLES, AND THE LATENCY TO THE AUXILIARY PORT IS 8.5 CLOCK CYCLES. ALL DATA PORTS ARE UPDATED ON THE RISING EDGE OF THE DREADY+ CLOCK.
Figure 18. Reset Output Timing in Demuxed DIV2 Mode (DREADY Aligned)
22
______________________________________________________________________________________
5V, 600Msps, 8-Bit ADC with On-Chip 2.2GHz Bandwidth Track/Hold Amplifier MAX106
ADC SAMPLE NUMBER CLKCLK CLK+ RESET INPUT n n+1 tSU RSTINRSTIN+ DREADY+ DREADY DREADYAUXILIARY DATA PORT PRIMARY DATA PORT RESET OUT DATA PORT RSTOUTRSTOUT+ n-2 OUT-OF-SEQUENCE SAMPLE n n+2 n+2 n+3 ADC SAMPLES ON THE RISING EDGE OF CLK+ n+4 n+5 n+6 n+7 n+8 n+9 n+10 n+11 n+12 n+13
tHD
CLOCK PULSE "SWALLOWED"
n-1
n+1
n+4
NOTE: DREADY PHASE WAS ADJUSTED TO MATCH THE RESET PHASE BY "SWALLOWING" ONE INPUT CLOCK CYCLE. THE AUXILIARY PORT CONTAINS AN OUT-OF-SEQUENCE SAMPLE AS A RESULT OF THE DELAY.
Figure 19. Reset Output Timing in Demuxed DIV2 Mode (DREADY Realigned)
asserted, the auxiliary port contained "even" samples while the primary port contained "odd" samples. After RSTOUT is deasserted (which marks the start of the DREADY clock's reset phase), note that the order of the samples in the ports has been reversed. The auxiliary port also contains an out-of-sequence sample. This is a consequence of the "swallowed" clock cycle that was needed to resynchronize DREADY to the reset phase. Also note that the older sample data is always in the auxiliary port, regardless of the DREADY phase. These examples show the combinations that result with a reset input signal of two clock cycles. It is also possible to successfully reset the internal MAX106 demux with a reset pulse only one clock cycle long, proving the setup-time and hold-time requirements are met with respect to the sample clock. However, this is not recommended when additional external demuxes are used. Note that many external demuxes require their reset signals to be asserted while they are clocked, and may require more than one clock cycle of reset. More importantly, if the phase of the DREADY clock is such that a clock pulse will be "swallowed" to resynchronize, then
no reset output will occur at all. In effect, the RSTOUT signal will be "swallowed" along with the clock pulse. The best method to ensure complete system reset is to assert RSTIN for the appropriate number of DREADY clock cycles required to complete reset of the external demuxes.
Die Temperature Measurement
For applications that require monitoring of the die temperature, it is possible to determine the die temperature of the MAX106 under normal operating conditions by observing the currents ICONST and IPTAT, at contacts ICONST and IPTAT. ICONST and IPTAT are two 100A (nominal) currents that are designed to be equal at +27C. These currents are derived from the MAX106's internal precision +2.5V bandgap reference. ICONST is designed to be temperature independent, while IPTAT is directly proportional to the absolute temperature. These currents are derived from pnp current sources referenced from VCCI and driven into two series diodes connected to GNDI. The contacts ICONST and IPTAT may be left open because internal catch diodes prevent saturation of the current sources. The simplest method of
______________________________________________________________________________________
23
5V, 600Msps, 8-Bit ADC with On-Chip 2.2GHz Bandwidth Track/Hold Amplifier MAX106
determining the die temperature is to measure each current with an ammeter (which shuts off the internal catch diodes) referenced to GNDI. The die temperature in C is then calculated by the expression: I TDIE = 300 PTAT - 273 ICONST Another method of determining the die temperature uses the operational amplifier circuit shown in Figure 20. The circuit produces a voltage that is proportional to the die temperature. A possible application for this signal is speed control for a cooling fan to maintain constant MAX106 die temperature. The circuit operates by converting the ICONST and IPTAT currents to voltages VCONST and VPTAT, with appropriate scaling to account for their equal values at +27C. This voltage difference is then amplified by two amplifiers in an instrumentation-amplifier configuration with adjustable gain. The nominal value of the circuit gain is 4.5092V/V. The gain of the instrumentation amplifier is given by the expression:
AV = VTEMP VCONST - VPTAT R1 R1 +2 R2 R3
To calibrate the circuit, first connect pins 2-3 on JU1 to zero the input of the PTAT path. With the MAX106 powered up, adjust potentiometer R3 until the voltage at the VTEMP output is -2.728V. Connecting pins 1-2 on JU1 restores normal operation to the circuit after the calibration is complete. The voltage at the VTEMP node will then be proportional to the actual MAX106 die temperature according to the equation: TDIE (C) = 100 VTEMP The overall accuracy of the die temperature measurement using the operational-amplifier scaling circuitry is limited mainly by the accuracy and matching of the resistors in the circuit.
Thermal Management
Depending on the application environment for the ESBGA-packaged MAX106, the customer may have to apply an external heatsink to the package after board assembly. Existing open-tooled heatsinks are available from standard heatsink suppliers (listed in Heatsink Manufacturers). The heatsinks are available with preapplied adhesive for easy package mounting.
AV = 1 +
3.32k 6.65k R1 7.5k JU1 1 12.1k 6.65k 2 3 VPTAT 12.1k
5k
10-TURN
R2 15k R2 15k R1 7.5k
IPTAT
1/4 MAX479
1/4 MAX479
ICONST VCONST VTEMP
1/4 MAX479
1/4 MAX479
6.05k
Figure 20. Die Temperature-Acquisition Circuit with the MAX479
24
______________________________________________________________________________________
5V, 600Msps, 8-Bit ADC with On-Chip 2.2GHz Bandwidth Track/Hold Amplifier MAX106
Table 7. Thermal Performance for MAX106 With or Without Heatsink
AIRFLOW (linear ft/min) 0 200 400 800 MAX106 JA (C/W) WITHOUT HEATSINK 16.5 14.3 13 12.5 WITH HEATSINK 12.5 9.4 8.3 7.4
JA (C/W)
THERMAL RESISTANCE vs. AIRFLOW
18 16 14 12 10 WITH HEATSINK 8 6
WITHOUT HEATSINK
Thermal Performance The MAX106 has been modeled to determine the thermal resistance from junction to ambient. Table 7 lists the ADC's thermal performance: Ambient Temperature: TA = +70C Heatsink Dimensions: 25mm x 25mm x 10mm PC Board Size and Layout: 4in. x 4in. 2 Signal Layers 2 Power Layers Heatsink Manufacturers Aavid Engineering and IERC provide open-tooled, lowprofile heatsinks, fitting the 25mm x 25mm ESBGA package. Aavid Engineering, Inc. Phone: 714-556-2665 Heatsink Catalog No.: 335224B00032 Heatsink Dimensions: 25mm x 25mm x 10mm
International Electronic Research Corporation (IERC) Phone: 818-842-7277 Heatsink Catalog No.: BDN09-3CB/A01 Heatsink Dimensions: 23.1mm x 23.1mm x 9mm
0
100 200 300 400 500 600 700 800 AIRFLOW (linear ft./min.)
Figure 21. MAX106 Thermal Performance
Bypassing/Layout/Power Supply
Grounding and power-supply decoupling strongly influence the MAX106's performance. At 600MHz clock frequency and 8-bit resolution, unwanted digital crosstalk may couple through the input, reference, power-supply, and ground connections and adversely influence the dynamic performance of the ADC. Therefore, closely follow the grounding and power-supply decoupling guidelines (Figure 22). Maxim strongly recommends using a multilayer printed circuit board (PCB) with separate ground and powersupply planes. Since the MAX106 has separate analog
and digital ground connections (GNDA, GNDI, GNDR, and GNDD, respectively), the PCB should feature separate analog and digital ground sections connected at only one point (star ground at the power supply). Digital signals should run above the digital ground plane, and analog signals should run above the analog ground plane. Keep digital signals far away from the sensitive analog inputs, reference inputs, and clock inputs. Highspeed signals, including clocks, analog inputs, and digital outputs, should be routed on 50 microstrip lines such as those employed on the MAX106 evaluation kit. The MAX106 has separate analog and digital powersupply inputs: VEE (-5V analog and substrate supply) and VCCI (+5V) to power the T/H amplifier, clock distribution, bandgap reference, and reference amplifier; V CCA (+5V) to supply the ADC's comparator array; VCCO (+3V to VCCD) to establish power for all PECLbased circuit sections; and VCCD (+5V) to supply all logic circuits of the data converter. The MAX106 V EE supply contacts must not be left open while the part is being powered up. To avoid this condition, add a high-speed Schottky diode (such as a Motorola 1N5817) between VEE and GNDI. This diode prevents the device substrate from forward biasing, which could cause latchup.
______________________________________________________________________________________
25
5V, 600Msps, 8-Bit ADC with On-Chip 2.2GHz Bandwidth Track/Hold Amplifier MAX106
All supplies should be decoupled with large tantalum or electrolytic capacitors at the point they enter the PCB. For best performance, bypass all power supplies to the appropriate ground with a 10F tantalum capacitor to filter power-supply noise, in parallel with a 0.01F capacitor and a high-quality 47pF ceramic chip capacitor located very close to the MAX106 device, to filter very high-frequency noise. straight line can be either a best-straight-line fit or a line drawn between the endpoints of the transfer function, once offset and gain errors have been nullified. The static linearity parameters for the MAX106 are measured using the best-straight-line fit method.
Static Parameter Definitions
Integral Nonlinearity Integral nonlinearity (INL) is the deviation of the values on an actual transfer function from a straight line. This
Differential Nonlinearity Differential nonlinearity (DNL) is the difference between an actual step width and the ideal value of 1LSB. A DNL error specification of less than 1LSB guarantees no missing codes and a monotonic transfer function.
VCCO
GNDD
10F
10nF
10nF
47pF
47pF
47pF
47pF
NOTE: LOCATE ALL 47pF CAPACITORS AS CLOSE AS POSSIBLE TO THE MAX106 DEVICE.
VCCI
GNDI
10F
10nF
10nF
47pF
47pF
47pF
47pF
VEE VCCA 1N5817 GNDI GNDA 10F 10nF 10nF 47pF 47pF VCCA = +4.75V TO +5.25V VCCD = +4.75V TO +5.25V VCCI = +4.75V TO +5.25V VCCO = +3.0V TO VCCD VEE = -4.75V TO -5.25V 10F 10nF 10nF 47pF 47pF 47pF 47pF 10F 10nF 10nF 47pF 47pF 47pF 47pF
VCCD
GNDD
Figure 22. MAX106 Bypassing and Grounding
26
______________________________________________________________________________________
5V, 600Msps, 8-Bit ADC with On-Chip 2.2GHz Bandwidth Track/Hold Amplifier
Bit Error Rates (BERs) Errors resulting from metastable states may occur when the analog input voltage (at the time the sample is taken) falls close to the decision point of any one of the input comparators. Here, the magnitude of the error depends on the location of the comparator in the comparator network. If it is the comparator for the MSB, the error will reach full scale. The MAX106's unique encoding scheme solves this problem by virtually eliminating these errors. Total Harmonic Distortion Total harmonic distortion (THD) is the ratio of the RMS sum of the first five harmonics of the input signal to the fundamental itself. This is expressed as:
THD = 20 log V22 + V32 + V4 2 + V52 / V1
MAX106
Dynamic Parameter Definitions
Signal-to-Noise Ratio For a waveform perfectly reconstructed from digital samples, the theoretical maximum (SNR) is the ratio of the full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum analog-to-digital noise is caused by quantization error only and results directly from the ADC's resolution (N bits):
SNR (max) = (6.02 * N + 1.76) dB In reality, there are other noise sources besides quantization noise: thermal noise, reference noise, clock jitter, etc. SNR is computed by taking the ratio of the RMS signal to the RMS noise, which includes all spectral components minus the fundamental, the first five harmonics, and the DC offset.
where V1 is the fundamental amplitude, and V2 through V5 are the amplitudes of the 2nd- through 5th-order harmonics.
Spurious-Free Dynamic Range Spurious-free dynamic range (SFDR) is the ratio, expressed in decibels, of the RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next-largest spurious component, excluding DC offset. Intermodulation Distortion The two-tone intermodulation distortion (IMD) is the ratio, expressed in decibels, of either input tone to the worst 3rd-order (or higher) intermodulation products. The input tone levels are at -7dB full scale.
Chip Information
TRANSISTOR COUNT: 20,486 SUBSTRATE CONNECTED TO VEE
Effective Number of Bits ENOB indicates the global accuracy of an ADC at a specific input frequency and sampling rate. An ideal ADC's error consists of quantization noise only. ENOB is computed from a curve fit referenced to the theoretical full-scale range. Signal-to-Noise Plus Distortion Signal-to-noise plus distortion (SINAD) is computed from the ENOB as follows:
SINAD = (6.02 * ENOB) + 1.76
______________________________________________________________________________________
27
5V, 600Msps, 8-Bit ADC with On-Chip 2.2GHz Bandwidth Track/Hold Amplifier MAX106
Typical Operating Circuit
+5V ANALOG -5V ANALOG +5V DIGITAL VEE DIVSELECT VCCA VCCI
+3.3V DIGITAL
Z0 = 50 50 VCCO - 2V 2 OR
ALL OUTPUTS MUST BE TERMINATED LIKE THIS.
VCCD AUXEN1 VCCO AUXEN2
+5V
DEMUXEN VOSADJ
2 P7 2 P6 2 P5
DIFFERENTIAL ANALOG INPUT 500mVp-p FS
Z0 = 50 Z0 = 50
VIN+ VINPRIMARY PECL OUTPUTS
2 P4 2 P3 2 P2 2 P1 TO MEMORY OR DIGITAL SIGNAL PROCESSOR
SAMPLE CLOCK 600MHz +4dBm
MAX106
Z0 = 50 CLK+
2 P0
CLK50
2 A7 2 A6 2 A5
GNDI CLKCOM AUXILARY PECL OUTPUTS 2 A4 2 A3 2 A2 2 A1 2 A0 RSTIN+ RSTINDREADY RSTOUT 2 2
GNDI
GNDA GNDR GNDI
GNDD REFOUT REFIN
28
______________________________________________________________________________________
5V, 600Msps, 8-Bit ADC with On-Chip 2.2GHz Bandwidth Track/Hold Amplifier
192-Contact ESBGA PCB Land Pattern
TOP VIEW
MAX106 192 Ball ESBGA Printed Circuit Board (PCB) Land Pattern
MAX106
MAX106
______________________________________________________________________________________
29
5V, 600Msps, 8-Bit ADC with On-Chip 2.2GHz Bandwidth Track/Hold Amplifier MAX106
Package Information
SUPER BGA.EPS 30 ______________________________________________________________________________________
5V, 600Msps, 8-Bit ADC with On-Chip 2.2GHz Bandwidth Track/Hold Amplifier
Package Information (continued)
MAX106
______________________________________________________________________________________
31
5V, 600Msps, 8-Bit ADC with On-Chip 2.2GHz Bandwidth Track/Hold Amplifier MAX106
NOTES
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
32 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 1999 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

▲Up To Search▲

Price & Availability of MAX106

	To Download MAX106 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .